Towards URLLC with srsRAN

This page presents latency analysis and improvement in radio access networks using the srsRAN software. Last updated on November 26, 2024.

Feel free to contact me if you have any queries or would like to request access to my master's thesis.

1 Background

1.1 Radio Access Network

The 5G network consists of two subsystems: the Radio Access Network (RAN) and the Mobile Core.

The RAN corresponds to a distributed set of base stations (named gNB).
The Mobile Core provides and ensures Internet connectivity.

1.2 gNB’s Data Processing Pipeline

The functionality of a gNB can be split into the Radio Unit (RU), Distributed Unit (DU), and Central Unit (CU).

The Radio Link Control (RLC) layer handles segmentation and reassembly.
The Medium Access Control (MAC) layer handles all real-time scheduling regarding resource allocation.
The (upper and lower) physical (PHY) layer handles (de)coding and (de)modulation.
The radio head (RH) converts radio frequency signals into samples and vice versa.

1.3 5G Frame Structure

The 5G frame structure is designed to be more flexible than its predecessors.
At the heart of this design is the concept of numerology, labelled by µ.

For instance, setting µ = 1, each slot has a duration of 0.5 ms.

2 Latency Analysis

2.1 Functionality of Radio Units

The RU-downlink (DL) processor performs OFDM modulation .

It converts DL frequency-domain symbols into DL time-domain samples.

The RU-uplink (UL) processor performs OFDM demodulation .

It converts UL time-domain samples into UL frequency-domain symbols.

2.2 Latency in Radio Units

① When RH slot s begins, the RH receives the UL signal from the air, converts it into UL samples, and then forwards them to the software interface.
② After a short time, the RU-UL processor receives these samples for UP slot s from the software interface and demodulates them into UL symbols.
③ In DP slot s + H, the RU-DL processor first waits for the RU-UL processor to finish the reception and processing in UP slot s. It then prepares DL samples for DP slot s + H and forwards them to the software interface. After this, the software interface forwards these DL samples to the RH.
④ There exists an H-slot offset between the RU-DL processor and the RH, implemented for DL radio preparation time (e.g., USB and RF chain).

2.3 Functionality of Distributed Units

The DU processor reads DL segments from the RLC layer and converts them into DL frequency-domain symbols, and vice versa.
It handles all real-time scheduling regarding physical resource allocation.

2.4 Latency in Distributed Units (Downlink)

① When the RU-DL processor finishes preparing DL samples for DP slot s + H − 1, it notifies the DU processor of the beginning of DU slot s + H + M. When it receives the notification, the DU processor first decides on resource allocation for DL transmission and/or UL reception.
② If the current DU slot is a DL slot, the DU processor then reads DL segments from the RLC layer and converts them into DL symbols.
③ These symbols wait in the computer’s memory and will be accessed by the RU-DL processor after M slots, i.e., at the end of DP slot s + H + M.
There exists an M-slot offset between the RU-DL processor and the DU processor, it is used by the DU processor to prepare resource allocation results and DL frequency-domain symbols in advance. This offset provides a margin for handling unexpected slowdowns in the DU processor , thus ensuring the uninterrupted operation of the RU-DL processor.

2.5 An Example for the Case of M = 1

In DU slot s + 2, a sudden slowdown in the DU’s execution occurs. The execution time in this DU slot is much longer than usual.
As the DU processor prepares the DL symbols one slot in advance, the RU-DL processor can still access the symbols at the end of DP slot s + 2.
The time offset restores once the DU resumes normal execution.

2.6 Latency in Distributed Units (Uplink)

④ When the RU-UL processor finishes preparing UL symbols for UP slot s, it forwards these symbols to the DU processor immediately.
⑤ Using the resource allocation results decided (H + M) slots ago (in DU slot s), the DU processor converts the UL symbols into UL segments.

2.7 Summary of Slot Offsets

At any given time point, there exist an H-slot offset and an M-slot offset.

The H-slot offset is between the RU-DL processor and the RH.
The M-slot offset is between the DU processor and the RU-DL processor.

These offsets arise from system implementation considerations.

2.8 Sources of Latency

The latency introduced by system implementation: H-slot and M-slot offsets
The latency introduced by 5G specifications:

Scheduling Request (SR): When a UE has UL data to send, it first sends an SR to the gNB. The gNB then schedules and sends an UL grant to the UE. The UE transmits the UL data to the gNB after receiving the UL grant.
Time Division Duplex (TDD): The TDD uses the same frequency band for both DL and UL transmissions. Each slot within a TDD period is thus specifically designated to be DL, UL, or mixed.

2.9 Latency Breakdown (srsRAN)

Steps ③ to ⑤: DL one-way latency > (H + M + 1) × 0.5 ms = 2.5 ms
Steps ① to ⑥: UL one-way latency > 9 × 0.5 ms = 4.5 ms
* K2 (in slots) represents the time delay between a DCI slot and the corresponding PUSCH slot, allowing UEs to prepare PUSCH data.

3 Latency Improvement

3.1 Latency in Radio Units (Recall)

The RU-DL processor always prepares DL samples at the end of a DP slot.

This introduces extra latency if these DL symbols are ready at the beginning of a DP slot or even earlier.

H is a constant and cannot be adjusted (e.g., H = 3 for Numerology 1).

3.2 Preparing Samples in Advance (M1)

Instead of waiting for the RU-UL processor, the RU-DL processor prepares DL samples at the beginning of a DP slot.

This allows the RU-DL processor to prepare DL samples in advance.

H can be adjusted through external configuration (e.g., H = 1).

3.3 Latency Breakdown (M1)

Steps ③ to ⑤: DL one-way latency > (H + M + 1) × 0.5 ms = 1.5 ms
Steps ① to ⑥: UL one-way latency > 9 × 0.5 ms = 4.5 ms

3.4 Event-Driven Symbol Transforming (M2)

① When DU slot s begins, the DU processor starts to prepare resource allocation results and DL symbols.
② In the meantime, the RU-DL processor enters a busy-waiting state.

The RU-DL processor keeps checking if the DL symbols are ready.

③ Once the condition is met, the RU-DL processor accesses the DL symbols.

3.5 Latency Breakdown (M1 + M2)

Steps ③ to ⑤: DL one-way latency > (H + M + 1) × 0.5 ms = 1 ms
Steps ① to ⑥: UL one-way latency > 9 × 0.5 ms = 2.5 ms

4 Evaluation

4.1 Latency Results: Baseline (srsRAN)

The DL one-way latency mainly spans from 3 ms and 4.5 ms.
The UL one-way latency mainly spans from 6 ms to 8.5 ms.
The results comply with the lower bounds 2.5 ms and 4.5 ms.

4.2 Latency Results: Baseline vs M1 (Preparing Samples in Advance)

The distribution of the DL one-way latency has shifted to the left by 1 ms.
The distribution of the UL one-way latency remains unchanged.
The results comply with the lower bounds 1.5 ms and 4.5 ms.

4.3 Latency Results: Baseline vs M1 + M2 (Event-Driven Symbol Transforming)

The distribution of the DL one-way latency has shifted to the left by 1.5 ms .
The distribution of the UL one-way latency has shifted to the left by 2 ms.
The results comply with the lower bounds 1 ms and 2.5 ms.

4.4 Overall Comparison

We improve one-way latency for DL by 40.67% and for UL by 26.75%.
The previous results validate both our latency analysis and improvement.